The present invention relates to a data processing apparatus and method for executing a stream of instructions out-of-order with respect to original program order.
A stream of instructions will have an initial program order, and certain data processing systems are arranged merely to execute the stream of instructions in that original program order. In order to seek to increase performance, data processing systems have been developed that are able to execute instructions out-of-order with respect to original program order. However, when reordering instructions for execution, care has to be taken to ensure that the dependencies between instructions are taken into account. For example, one instruction may need to read as a source operand the contents of a register that is to be written to by an instruction earlier in the instruction stream. It should hence read that register's contents only after the previous instruction has written to the register. Such a dependency is known as a read after write (RAW) hazard. However, there are also other dependencies that occur with respect to the source and destination registers of instructions, such as a write after write (WAW) hazard and a write after read (WAR) hazard. In addition, other dependencies may also exist in the instruction stream. For example, some instructions may be conditionally executed, and as a result it will not be known whether certain later instructions actually need to be executed or not until such conditional instructions have been executed. Such dependencies will be referred to herein as speculation hazards. As another example, certain structural hazards will also exist, in situations where an instruction must stall because the next stage in the processing pipeline is occupied.
In data processing systems that are designed to execute instructions out-of-order, various hardware structures are typically provided which aim to eliminate certain of the hazards that can otherwise restrict the ability to reorder instructions. In particular, the hazards that are eliminated through use of the out-of-order hardware components will be referred to herein as false hazards (or false dependencies). Conversely, any remaining hazards which are not eliminated by the out-of-order hardware components will be referred to herein as true hazards (or true dependencies).
Two types of false hazards which can be removed by such out-of-order hardware components are the earlier mentioned WAR and WAW hazards. These can be addressed by employing as one of the out-of-order hardware components register renaming circuitry to map the architectural registers specified by the instructions to a larger set of buffer entries within a result buffer, the result buffer also forming one of the out-of-order hardware components. Further, another out-of-order hardware component that is often provided is a reorder buffer, which in combination with the result buffer can be used to remove speculation hazards as another form of false hazard. To deal with structural hazards (another false hazard), an issue queue is typically used, providing a window of instructions that can be issued for execution, effectively the issue circuitry being able to issue instructions dynamically from anywhere in the instruction window. By removing such false dependencies, the out-of-order hardware components then provide a great deal of flexibility as to how the instructions are reordered in order to seek to improve performance of the data processing apparatus. All that remains is to check for any true dependencies, and ensure that those true dependencies are no longer present in respect of any instructions issued. An example of a true dependency is the earlier mentioned RAW dependency.
Whilst such out-of-order hardware components provide the above benefits, they are relatively costly to implement, and consume significant energy. In addition, to improve performance further, it is typically necessary to increase the size of these out-of-order hardware components, to effectively increase the size of the instruction window from which instructions can be selected for execution.
It would be desirable to provide an improved mechanism for executing a stream of instructions out-of-order with respect to original program order, which enabled improved performance and/or energy savings when compared with the above described known technique.